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The document addresses how to set up the SGLang environment and run LLM inference on Intel GPU, see more context about Intel GPU support within PyTorch ecosystem. Specifically, SGLang is optimized for Intel® Arc™ Pro B-Series Graphics and Intel® Arc™ B-Series Graphics.

Optimized Model List

A list of LLMs have been optimized on Intel GPU, and more are on the way:
Model NameBF16
Llama-3.2-3Bmeta-llama/Llama-3.2-3B-Instruct
Llama-3.1-8Bmeta-llama/Llama-3.1-8B-Instruct
Qwen2.5-1.5BQwen/Qwen2.5-1.5B
Note: The model identifiers listed in the table above have been verified on Intel® Arc™ B580 Graphics. Quantized MoE models are covered separately in MXFP4 MoE Quantization below.

Installation

Install From Source

Currently SGLang XPU only supports installation from source. Please refer to “Getting Started on Intel GPU” to install XPU dependency.
Command

Install Using Docker

The SGLang XPU Dockerfile is provided to facilitate the installation. Replace <secret> below with your HuggingFace access token.
Command

Launch of the Serving Engine

Example command to launch SGLang serving:

MXFP4 MoE Quantization

Native MXFP4 MoE checkpoints (OCP microscaling FP4: packed e2m1 weights plus per-32-element ue8m0 block scales) run on Intel GPUs through the sgl-kernel-xpu W4A16 grouped GEMM. The expert weights stay in the checkpoint’s packed layout end to end — there is no dequantization to BF16 — so GPT-OSS-20B loads in roughly 13 GB rather than the ~42 GB a BF16 upcast would need, which is what lets it fit on a single 24 GB card. The mxfp4 method is registered automatically on --device xpu, which already requires sgl-kernel-xpu — no extra flag is needed:
Tested models: Requirements and limitations:

Benchmarking with Requests

You can benchmark the performance via the bench_serving script. Run the command in another terminal.
The detail explanations of the parameters can be looked up by the command:
Additionally, the requests can be formed with OpenAI Completions API and sent via the command line (e.g. using curl) or via your own script.

XPU Graph [Experimental]

SGLang enables XPU graph capture to reduce per-step kernel-launch overhead.

Enable Decode Graph

Decode graph capture is opt-in on XPU. Enable it explicitly:

Enable Prefill Graph

Prefill graph capture is opt-in on XPU and must be enabled explicitly. Two backends are available: tc_piecewise and breakable.

tc_piecewise

Uses torch.compile plus an XPU graph, one graph segment per token-length bucket:
By default the prefill subgraphs are compiled with eager mode. Switch to inductor for higher-quality generated code at the cost of longer startup:

breakable

Captures the transformer stack as segmented XPUGraphs with eager break points at attention / MoE boundaries, without torch.compile:
You can also configure both phases together with a single --cuda-graph-config JSON argument:

Enable torch.compile for Decode

--enable-torch-compile adds a torch.compile pass on top of the decode XPU graph: the model forward is compiled first, and the compiled forward is then captured as an XPUGraph. This can reduce per-kernel overhead further but increases startup time.
Note: --enable-torch-compile is mutually exclusive with the prefill tc_piecewise graph (the compatibility rules auto-disable it). Use them separately or lock the prefill backend explicitly via --cuda-graph-config if you need both.

Disable XPU Graph

Both phases are disabled by default. To explicitly disable them anyway:

Customize Capture Buckets

By default, prefill capture sizes are derived from --chunked-prefill-size. To specify explicit token-length buckets:
To specify explicit decode graph batch sizes:

Server Args

* Prefill graph is auto-disabled on XPU unless you lock the backend explicitly via --cuda-graph-backend-prefill or --cuda-graph-config.

Limitations

Memory Saver (release/resume memory occupation) on Intel XPU [Experimental]

SGLang can temporarily release most of the GPU memory it holds — model weights and/or KV cache — and reclaim it later without restarting the process. This is the same release_memory_occupation / resume_memory_occupation feature available on CUDA, used for RL rollout/training hand-off and for freeing the device between inference bursts. This is backed by the torch_memory_saver package — the same package used on CUDA — which gained an Intel XPU backend built natively on Level Zero (keeping virtual addresses fixed while releasing/re-committing physical pages via zeVirtualMemUnmap / zeVirtualMemMap). Install torch_memory_saver. Unlike CUDA (prebuilt wheel), the XPU backend is built from source against your local oneAPI + torch+xpu runtime (the .so links libsycl.so.<N>, which must match the installed intel-sycl-rt). TMS_PLATFORM=xpu forces the XPU backend, and --no-build-isolation lets the build import your installed torch so it can match the libsycl major to it: The published wheels are CUDA-only, so install from git and let it build. The ref below is the v0.0.10b2 release, pinned so the build is reproducible.
Use it by launching with --enable-memory-saver (the XPU backend is selected automatically); optionally add --enable-weights-cpu-backup to keep weights in host RAM across a release:
The Python engine API (engine.release_memory_occupation(tags=...) / engine.resume_memory_occupation(tags=...)) and the weights / kv_cache tags behave the same as on CUDA. Pauseable CUDA-graph capture is not used on XPU, so the cuda_graph tag is a no-op there.
Verifying memory was freed: neither torch.xpu.memory_allocated() nor torch.xpu.mem_get_info() drops when physical pages are released — the first is allocator accounting, and the second stays flat because torch keeps the freed block cached. Query actual device memory via sysman (ZES_ENABLE_SYSMAN=1) instead.

Prefill-Decode (P/D) Disaggregation on Intel XPU [Experimental]

SGLang supports prefill-decode disaggregation on Intel XPU using the NIXL KV-transfer backend. Tested models: Prerequisites: pip install nixl sglang-router Start the prefill server (GPU 0):
Start the decode server (GPU 1):
Start the router:
Send a request:
Note: UCX_POSIX_USE_PROC_LINK=n is required on Intel XPU to avoid UCX shared-memory transport issues.