Optimized Model List
A list of LLMs have been optimized on Intel GPU, and more are on the way:| Model Name | BF16 |
|---|---|
| Llama-3.2-3B | meta-llama/Llama-3.2-3B-Instruct |
| Llama-3.1-8B | meta-llama/Llama-3.1-8B-Instruct |
| Qwen2.5-1.5B | Qwen/Qwen2.5-1.5B |
Installation
Install From Source
Currently SGLang XPU only supports installation from source. Please refer to “Getting Started on Intel GPU” to install XPU dependency.Command
Install Using Docker
The SGLang XPU Dockerfile is provided to facilitate the installation. Replace<secret> below with your HuggingFace access token.
Command
Launch of the Serving Engine
Example command to launch SGLang serving:MXFP4 MoE Quantization
Native MXFP4 MoE checkpoints (OCP microscaling FP4: packede2m1 weights plus
per-32-element ue8m0 block scales) run on Intel GPUs through the
sgl-kernel-xpu W4A16 grouped GEMM. The expert weights stay in the checkpoint’s
packed layout end to end — there is no dequantization to BF16 — so GPT-OSS-20B
loads in roughly 13 GB rather than the ~42 GB a BF16 upcast would need, which is
what lets it fit on a single 24 GB card.
The mxfp4 method is registered automatically on --device xpu, which already
requires sgl-kernel-xpu — no extra flag is needed:
Requirements and limitations:
Benchmarking with Requests
You can benchmark the performance via thebench_serving script.
Run the command in another terminal.
curl) or via your own script.
XPU Graph [Experimental]
SGLang enables XPU graph capture to reduce per-step kernel-launch overhead.Enable Decode Graph
Decode graph capture is opt-in on XPU. Enable it explicitly:Enable Prefill Graph
Prefill graph capture is opt-in on XPU and must be enabled explicitly. Two backends are available:tc_piecewise and breakable.
tc_piecewise
Usestorch.compile plus an XPU graph, one graph segment per token-length
bucket:
eager mode. Switch to
inductor for higher-quality generated code at the cost of longer startup:
breakable
Captures the transformer stack as segmentedXPUGraphs with eager break points
at attention / MoE boundaries, without torch.compile:
--cuda-graph-config JSON argument:
Enable torch.compile for Decode
--enable-torch-compile adds a torch.compile pass on top of the decode
XPU graph: the model forward is compiled first, and the compiled forward is
then captured as an XPUGraph. This can reduce per-kernel overhead further
but increases startup time.
Note:--enable-torch-compileis mutually exclusive with the prefilltc_piecewisegraph (the compatibility rules auto-disable it). Use them separately or lock the prefill backend explicitly via--cuda-graph-configif you need both.
Disable XPU Graph
Both phases are disabled by default. To explicitly disable them anyway:Customize Capture Buckets
By default, prefill capture sizes are derived from--chunked-prefill-size.
To specify explicit token-length buckets:
Server Args
* Prefill graph is auto-disabled on XPU unless you lock the backend explicitly
via
--cuda-graph-backend-prefill or --cuda-graph-config.
Limitations
Memory Saver (release/resume memory occupation) on Intel XPU [Experimental]
SGLang can temporarily release most of the GPU memory it holds — model weights and/or KV cache — and reclaim it later without restarting the process. This is the samerelease_memory_occupation / resume_memory_occupation feature
available on CUDA, used for RL rollout/training hand-off and for freeing the
device between inference bursts.
This is backed by the torch_memory_saver
package — the same package used on CUDA — which gained an Intel XPU backend
built natively on Level Zero (keeping virtual addresses fixed while
releasing/re-committing physical pages via zeVirtualMemUnmap /
zeVirtualMemMap).
Install torch_memory_saver. Unlike CUDA (prebuilt wheel), the XPU backend
is built from source against your local oneAPI + torch+xpu runtime (the .so
links libsycl.so.<N>, which must match the installed intel-sycl-rt).
TMS_PLATFORM=xpu forces the XPU backend, and --no-build-isolation lets the
build import your installed torch so it can match the libsycl major to it:
The published wheels are CUDA-only, so install from git and let it build. The ref
below is the v0.0.10b2 release, pinned so the build is reproducible.
--enable-memory-saver (the XPU backend is
selected automatically); optionally add --enable-weights-cpu-backup to keep
weights in host RAM across a release:
engine.release_memory_occupation(tags=...) /
engine.resume_memory_occupation(tags=...)) and the weights / kv_cache tags
behave the same as on CUDA. Pauseable CUDA-graph capture is not used on XPU, so
the cuda_graph tag is a no-op there.
Verifying memory was freed: neithertorch.xpu.memory_allocated()nortorch.xpu.mem_get_info()drops when physical pages are released — the first is allocator accounting, and the second stays flat because torch keeps the freed block cached. Query actual device memory via sysman (ZES_ENABLE_SYSMAN=1) instead.
Prefill-Decode (P/D) Disaggregation on Intel XPU [Experimental]
SGLang supports prefill-decode disaggregation on Intel XPU using the NIXL KV-transfer backend. Tested models:
Prerequisites:
pip install nixl sglang-router
Start the prefill server (GPU 0):
Note: UCX_POSIX_USE_PROC_LINK=n is required on Intel XPU to avoid UCX shared-memory transport issues.
